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revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5V408B is a family of low voltage 4-Mbit static RAMs organized as 524,288-words by 8-bit, fabricated by Mitsubishi's highperformance 0.25m CMOS technology. The M5M5V408B is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5V408B is packaged in 32-pin plastic SOP, 32-pin plastic TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of TSOPs and two types of STSOPs are available, M5M5V408BTP (normal-lead-bend TSOP), M5M5V408BRT (reverse-lead-bend TSOP), M5M5V408BKV (normal-lead-bend STSOP) and M5M5V408BKR (reverse-lead-bend STSOP). These two types TSOPs and two types STSOPs are suitable for a surface mounting on double-sided printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below. FEATURES * Single +2.7~+3.6V power supply * Small stand-by current: 0.3A(3V,typ.) * No clocks, No refresh * Data retention supply voltage=2.0V to 3.6V * All inputs and outputs are TTL compatible. * Easy memory expansion by S * Common Data I/O * Three-state outputs: OR-tie capability * OE prevents data contention in the I/O bus * Process technology: 0.25m CMOS * Package: M5M5V408BFP: 32 pin 525 mil SOP M5M5V408BTP/RT: 32 PIN 400mil TSOP(ll) M5M5V408BKV/KR: 32 pin 8mm x13.4mm STSOP PART NAME TABLE Version, Operating temperature Part name (## stands for "FP","TP", "RT","KV"or"KR") M5M5V408B## -85L M5M5V408B## -10L M5M5V408B## -85H M5M5V408B## -10H M5M5V408B## -85LW Power Supply 2.7 ~ 3.6V 2.7 ~ 3.6V Access time Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 25C 40C 25C 40C 70C 85C ------1A --3A 20A 10A ----- max. 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns Active current Icc1 (3.0V, typ.) Standard 0 ~ +70C 0.3A 1A W-version -20 ~ +85C M5M5V408B## -10LW M5M5V408B## -85HW M5M5V408B## -10HW M5M5V408B## -85LI 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V --- --- --1A --1A --3A --3A 20A 40A 10A 20A 30mA (10MHz) 5mA (1MHz) 0.3A 1A ----- I-version -40 ~ +85C M5M5V408B## -10LI M5M5V408B## -85HI M5M5V408B## -10HI 20A 40A 10A 20A 0.3A 1A * "typical" parameter is sampled, not 100% tested. MITSUBISHI ELECTRIC 1 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 VCC A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND Outline 32P2M-A (FP) 32P3Y-H (TP) Outline 32P3Y-J (RT) A11 A9 A8 A13 W A18 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 M5M5V408BKV 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 A18 W A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 M5M5V408BKR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S A10 OE Outline 32P3K-B Outline 32P3K-C MITSUBISHI ELECTRIC 2 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The M5M5408BFP,TP,RT,KV,KR is organized as 524,288words by 8-bit. These devices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. A write operation is executed during the S low and W low overlap time. The address(A0~A18) must be set up before the write cycle A read operation is executed by setting W at a high level and OE at a low level while S are in an active state(S=L). When setting S at a high level, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. The power supply current is reduced as low as 0.3A(25C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. FUNCTION TABLE S H L L L W X L H H OE X X L H Mode Non selection Write Read Read DQ High-impedance Data input (D) Data output (Q) High-impedance Icc Standby Active Active Active Pin A0 ~ A18 Function Address input Chip select input Write control input Output inable input Power supply Ground supply DQ1 ~ DQ8 Data input / output S W OE Vcc GND BLOCK DIAGRAM M5M5V408B FP/TP/RT M5M5V408BKV/KR 16 15 14 13 12 11 10 9 6 7 21 22 M5M5V408BKV/KR A4 A5 A6 A7 A12 A14 A16 A17 A18 A15 A10 A11 A9 A8 A13 8 7 6 5 4 3 2 30 1 31 M5M5V408B FP/TP/RT 13 14 15 17 18 19 20 21 MEMORY ARRAY 524288 WORDS x 8 BITS 23 25 26 27 28 29 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 23 25 26 27 28 31 1 2 3 4 5 30 29 22 24 CLOCK GENERATOR W S OE VCC (3V) A0 A1 A2 A3 12 11 10 9 20 19 18 17 32 8 32 24 16 GND (0V) MITSUBISHI ELECTRIC 3 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C Standard W-version I-version Ratings Units Vcc VI VO Pd Ta Tstg (-L, -H) (-LW, -HW) (-LI, -HI) -0.5* ~ +4.6 -0.5* ~ Vcc + 0.5 0 ~ Vcc 700 0 ~ +70 -20 ~ +85 -40 ~ +85 -65 ~150 V mW C C * -3.0V in case of AC (Pulse width 30ns) DC ELECTRICAL CHARACTERISTICS Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage 1 IOH= -0.5mA High-level output voltage 2 IOH= -0.05mA Low-level output voltage Input leakage current Output leakage current Active supply current ( AC,MOS level ) Active supply current ( AC,TTL level ) Conditions ( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Min Typ Max Vcc+0.3V Units VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2 2.2 -0.3 * 2.4 Vcc-0.5V 0.6 V 0.4 1 1 IOL=2mA VI =0 ~ Vcc S=VIH or OE=VIH, VI/O=0 ~ Vcc S 0.2V Output-open Other inputs 0.2V or Vcc-0.2V Output-open S=VIL Other inputs=VIH or VIL -L, -LW, -LI f= 10MHz f= 1MHz f= 10MHz f= 1MHz -LW, -LI +70 ~ +85C +70C A - Icc3 Stand by supply current ( AC,MOS level ) -HW, -HI +70 ~ +85C +40 ~ +70C -H, -HW, -HI Other inputs=0~Vcc +25 ~ +40C -H 0 ~ +25C S Vcc-0.2V -HW -HI -20 ~ +25C -40 ~ +25C 30 5 30 5 1 0.3 0.3 0.3 - 40 7 40 7 48 24 24 12 3.6 1.2 1.2 1.2 0.5 mA A Icc4 Stand by supply current ( AC,TTL level ) S=V ,Other inputs= 0 ~ Vcc mA Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25C * -3.0V in case of AC (Pulse width 30ns) CAPACITANCE Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz (Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Typ Max Units Min CI CO 8 10 pF MITSUBISHI ELECTRIC 4 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS Supply voltage Input pulse Input rise time and fall time Reference level (Vcc=2.7 ~ 3.6V, unless otherwise noted) 2.7V~3.6V VIH=2.4V,VIL=0.4V 5ns VOH=VOL=1.5V Transition is measured 500mV from steady state voltage.(for ten,tdis) 1TTL DQ CL Including scope and jig capacitance Output loads Fig.1,CL=30pF CL=5pF (for ten,tdis) Fig.1 Output load (2) READ CYCLE Limits Symbol Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after S high Output disable time after OE high Output enable time after S low Output enable time after OE low Data valid time after address M5M5V408B FP,TP,RT,KV,KR-85 M5M5V408B FP,TP,RT,KV,KR-10 Units Min Max Min Max tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) 85 85 85 45 30 30 10 5 10 100 100 100 50 35 35 10 5 10 ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol Parameter Write cycle time Write pulse width Address set up time Address set up time with respect to W high Chip select set up time Data set up time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low M5M5V408B FP,TP,RT,KV,KR-85 M5M5V408B FP,TP,RT,KV,KR-10 Units Min Max Min Max tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) 85 60 0 70 70 35 0 0 30 30 5 5 100 75 0 85 85 40 0 0 35 35 5 5 ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI ELECTRIC 5 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle A0~18 ta(A) ta(S) S (Note3) tCR tv (A) tdis (S) ta (OE) (Note3) OE (Note3) W = "H" level ten (OE) ten (S) tdis (OE) (Note3) DQ1~8 VALID DATA Write cycle ( W control mode ) tCW A0~18 tsu (S) S (Note3) tsu (A-WH) (Note3) OE tsu (A) W tdis (W) tdis(OE) DQ1~8 DATA IN STABLE tw (W) trec (W) ten(OE) ten (W) tsu (D) th (D) MITSUBISHI ELECTRIC 6 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Write cycle (S control mode) tCW A0~18 tsu (A) S tsu (S) trec (W) (Note5) W (Note3) (Note4) (Note3) tsu (D) DQ1~8 DATA IN STABLE th (D) Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during the overlap of a low S and a low W. Note 5: If W goes low simultaneously with or prior to S,the output remains in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 7 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Test conditions Min Limits Typ Max Units V V Vcc (PD) Power down supply voltage Chip select input S VI (S) -LW, -LI +70 ~ +85C -L, -LW, -LI +70C -HW, -HI +70 ~ +85C Icc (PD) Power down supply current Vcc=3.0V, SVcc-0.2V, Other inputs=0 ~ Vcc -H, -HW, -HI -H -HW +40 ~ +70C +25 ~ +40C 0 ~ +25C -20 ~ +25C 2.0 2.0 - 1 0.3 0.3 0.3 -HI -40 ~ +25C 40 20 20 10 3 1 1 1 A A A A A A A A Typical value is for Ta=25C (2) TIMING REQUIREMINTS Symbol Parameter Power down set up time Power down recovery time Test conditions Limits Min 0 5 Typ Max Units ns ms tsu (PD) trec (PD) (3) TIMING DIAGRAM S control mode Vcc tsu (PD) 2.2V S SVcc - 0.2V 2.7V 2.7V trec (PD) 2.2V MITSUBISHI ELECTRIC 8 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Revision History Revision No. K0.1e K0.2e K1.0e History The first edition Added M5M5V408BFP/TP/RT The first product version Date '98.3.05 '98.7.30 '98.9.7 Preliminary Preliminary MITSUBISHI ELECTRIC 9 32P2M-A Plastic 32pin 525mil SOP Weight(g) 1.29 Lead Material Alloy 42 e b2 17 EIAJ Package Code SOP32-P-525-1.27 JEDEC Code - 32 HE E e1 Recommended Mount Pad Symbol 16 1 A F D A2 A1 L1 b y e L A A1 A2 b c D E e HE L L1 y c Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max - - 3.05 0 0.1 0.2 - 2.75 - 0.35 0.4 0.5 0.13 0.15 0.2 20.55 20.75 20.95 11.3 11.4 11.5 - 1.27 - 13.8 14.1 14.4 0.6 0.8 1.0 - 1.35 - - - 0.15 0 - 8 - 0.76 - - 13.34 - - 1.27 - I2 Mar.'98 32P3Y-H Plastic 32pin 400mil TSOP ( ) Weight(g) 0.53 e b2 Lead Material Alloy 42 EIAJ Package Code TSOPII 32-P-400-1.27 JEDEC Code - E HE 1 16 A c D L1 L e y b A2 A1 Detail F ME 32 17 Recommended Mount Pad Symbol A A1 A2 b c D E e HE L L1 y ME I2 b2 Dimension in Millimeters Min Nom Max - - 1.2 0.125 0.2 0.05 - - 1.0 0.35 0.4 0.5 0.105 0.125 0.175 20.85 20.95 21.05 10.16 10.26 10.06 - 1.27 - 11.76 11.56 11.96 0.5 0.4 0.6 0.8 - - - - 0.1 - 0 10 10.36 - - - - 0.9 - - 0.76 I2 Mar.'98 F 32P3Y-J Plastic 32pin 400mil TSOP ( ) Weight(g) 0.53 e b2 Lead Material Alloy 42 EIAJ Package Code TSOPII 32-P-400-1.27 JEDEC Code - HE E ME 1 16 Recommended Mount Pad Symbol 32 17 A c L1 L D e y b A2 Detail F A1 A A1 A2 b c D E e HE L L1 y ME I2 b2 Dimension in Millimeters Min Nom Max - - 1.2 0.125 0.2 0.05 - - 1.0 0.35 0.4 0.5 0.105 0.125 0.175 20.85 20.95 21.05 10.16 10.26 10.06 - 1.27 - 11.76 11.56 11.96 0.5 0.4 0.6 0.8 - - - - 0.1 - 0 10 10.36 - - - - 0.9 - - 0.76 I2 Mar.'98 F 32P3K-B Plastic 32pin 8!13.4mm TSOP( ) Weight(g) MD e b2 Lead Material Alloy 42 EIAJ Package Code - JEDEC Code - HD l2 e 32 D Recommended Mount Pad 1 y E Symbol 17 F A A2 b L1 16 c A A1 A2 b c D E e HD L L1 y A1 L Detail F b2 I2 MD Dimension in Millimeters Min Nom Max - - 1.2 0.05 0.125 0.2 - 1.0 - 0.15 0.2 0.3 0.13 0.15 0.2 11.7 11.8 11.9 7.9 8.0 8.1 - 0.5 - 13.2 13.4 13.6 0.4 0.5 0.6 - 0.8 - - - 0.1 0 - 10 - 0.225 - 0.9 - - 12.0 - - Mar.'98 32P3K-C Plastic 32pin 8!13.4mm TSOP( ) Weight(g) MD e b2 Lead Material Alloy 42 EIAJ Package Code - JEDEC Code - HD D e l2 Recommended Mount Pad y Symbol 32 1 E 16 F A b L1 A2 17 c A A1 A2 b c D E e HD L L1 y A1 L Detail F b2 I2 MD Dimension in Millimeters Min Nom Max - - 1.2 0.05 0.125 0.2 - 1.0 - 0.15 0.2 0.3 0.13 0.15 0.2 11.7 11.8 11.9 7.9 8.0 8.1 - 0.5 - 13.2 13.4 13.6 0.4 0.5 0.6 - 0.8 - - - 0.1 0 - 10 - 0.225 - 0.9 - - 12.0 - - Mar.'98 |
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